1. Field of the Invention
The present invention relates to a semiconductor device forming an LSI (large scale integrated circuit) containing bipolar transistors and CMOS transistors.
2. Description of the Related Art
A semiconductor device in which bipolar transistors and CMOS transistors are formed in a semiconductor substrate, conventionally, is formed in the following way. A plurality of N.sup.+ buried regions are selectively formed in a p-type silicon substrate. A P-type epitaxial layer of 2.0 to 5.0 .mu.m thick is selectively formed over the entire surface of the structure. N-well regions are formed in bipolar transistor forming regions and PMOS transistor forming regions. P-well regions are formed in NMOS transistor forming regions and bipolar transistor isolating regions. In forming the P-well and N-well regions, an ion implanting method and a lithography method are used for selective doping of impurities. Then, the structure is annealed at 1100.degree. C. or more for well diffusion. Thereafter, MOS transistors and bipolar transistor are formed in a usual manner.
FIG. 1 shows a sectional view of an LSI structure containing bipolar transistors and CMOS transistors that are formed by a conventional technique. FIG. 2 shows a profile of a distribution of impurity concentration in the N-well region for bipolar transistor and PMOS transistor. FIG. 3 shows a profile of a distribution of impurity concentration in the P-well region for an NMOS transistor. In FIG. 1, reference numeral 51 designates P-type semiconductor substrate; 52 an N.sup.+ buried region., 53 and 57 N-well regions, 54 element insulating region; 55 N.sup.+ buried lead electrode; 56 a P-well; 58 a gate oxide film; 59 a gate polycrystalline silicon layer; 60 an interlaying insulating film; 61 an emitter polycrystalline silicon layer; 62 an N.sup.+ emitter region, 63 internal base region; 64 a P field layer; 65 an N.sup.- region of the LDD structure; 66 an N.sup.+ region; 67 a P.sup.+ region; 68 an external base region; 69 a side wall for forming the N.sup.+ region; 70 an interlayer insulating film; and 71 an aluminum (Al) electrode.
In the LSI structure manufactured by the conventional technique, as the microfabrication of the MOS transistors further progresses, a concentration in the N-well region 57 of the PMOS transistor is increased in order to prevent occurrence of a short channel effect of the MOS transistor, for example. When a bipolar transistor is formed in the N-well region 53 that is formed simultaneously with the N-well region 57, an impurity concentration in the collector of the bipolar transistor increases. When the impurity concentration of the collector of the bipolar transistor increases, a breakdown voltage BV.sub.CB0 between the base and collector of the transistor and an early voltage V.sub.AF, which are fundamental performances of the bipolar transistor, are degraded. When the PMOS-FET gate length becomes shorter than 0.8 .mu.m, the degradation occurs.
When using the conventional technique, a P-type epitaxial layer is first formed, and the N-well regions 53 and 57 are formed in the epitaxial layer. In this case, the N-wells 53 and 57 must have impurity concentration profiles required for the PMOS transistor and the bipolar transistor. To this end, a well diffusion process is performed. When the well diffusion process is used, P.sup.+ buried regions 84 must be formed in the N-well regions 53 and 57 in order to prevent occurrence of a punch-through in those regions. In the structure containing the buried region 84, when the well diffusion process progresses, impurities are actively diffused from the buried region 84 toward the region located above the buried region. Such a diffusion will have an adverse effect on the characteristics of the MOS transistor. For the above reason, there is a limit increasing an impurity concentration of the P.sup.+ buried region.
When the well diffusion process is used for forming the collector of the bipolar transistor, a profile of an impurity concentration of the collector of the transistor has an inclination declining from the surface of the collector inwardly. Therefore, the bipolar characteristic is degraded in a high current region.
Accordingly, an object of the present invention is to provide a semiconductor device which can provide improved electric characteristics of bipolar transistors and MOS transistors even if those different types of transistors are formed in the same semiconductor substrate, and has a high soft error resistance.